I am a project scientist and recent PhD graduate in the ECE department at Carngie Mellon University. My research focuses on digital IC design, high performance computing, and hardware security. I was advised by Larry Pileggi and collaborate with Ken Mai, Shawn Blanton, and Marijn Heule.

Education

Carnegie Mellon University, Pittsburgh, Pennsylvania
PhD, MS Electrical and Computer Engineering 2021, 2017

• Awards: NSF Graduate Fellowship Honorable Mention, Carnegie Institute of Technology Dean's Fellow
• Coursework: Advanced Digital IC Design, Machine Learning, Computer Architecture, Reconfigurable Logic, Computational Models of Neural Systems, Neural Signal Processing, Numerical Methods and Optimization, Circuit Simulation, Digital System Testing

Columbia University, New York, New York
BS Electrical Engineering 2015

• Awards: Magna Cum Laude, Dean’s List
• Coursework: Solid State Devices, Signals and Systems, Electronic Circuits, Device Microfabrication, Modern Display Technology, Computer Networks, Data Structures, Computer Hardware Design, Digital VLSI Circuits, Advanced Programming, Nanotechnology

Experience

Carnegie Mellon University Student Researcher, Center for Silicon System Implementation 2015 to Present

• Developed low-overhead circuit obfuscation methods that hide design function through programmable elements.
• Lead multiple successful accelerator tape-outs in 28/22/16nm technology nodes conducting system design, RTL implementation, synthesis, PNR, formal verification, and IC testing.
• Built and maintained research group's synthesis, physical design, and verification flows.

Carnegie Mellon University Teaching Assistant, Department of Electrical and Computer Engineering 2018 to Present

• Advanced Digital Integrated Circuit Design: Established EDA flows and guided students in tape-out projects from development through IC testing.
• Reconfigurable Logic: Led recitations, developed labs in Vivado HLS/C++, and assisted students in class projects developing applications for FPGAs.
• Introduction to Electrical and Computer Engineering: Led recitations and wrote quizes to assess class understanding of lecture material.

Hewlett Packard VLSI/ASIC Engineering Intern, Enterprise Servers Division Summer 2014

• Created online scheduling system to automate stability testing for in-development ASICs.
• Produced and maintained Tcl/Bash EDA scripts.

Selected Projects

Analysis of Locked Circuits SAT, Python, Jasper Gold, Tessent, Genus

• Created attack techniques for reverse-engineering obfuscation schemes using formal methods such as SAT, ATPG, and model checking.
• Established logic modeling techniques that enable key extraction in seconds for circuits that were previously unbreakable within weeks of run time.
• Demonstrated how Boolean sensitivity analysis can be used to deobfuscate circuits locked with a class of “provably secure” logic locking techniques.
• Updated broken obfuscation techniques with solutions for resisting the novel attack methods.

Sparse Matrix-Vector Multiplication Accelerator Python, SystemVerilog, Genus, Innovus

• Taped out accelerator for a novel sparse matrix-vector multiplication algorithm, co-optimizing between algorithm and underlying hardware.
• Designed micro-architecture utilizing custom synthesizable memory blocks for fine grained data access and multiple clock domains for power conservation.
• Using SystemVerilog and Innovus, iteratively optimized the design parameters and floorplan.
• Showed more than an order of magnitude improvement over current custom hardware solutions and more than two orders of magnitude improvement over commercial off-the-shelf architectures for both performance and energy efficiency.

Latch-Based Logic Locking Genus, Innovus, Japser Gold, SystemVerilog, Tcl, Tessent

• Created a circuit obfuscation method that manipulates the clock phase of sequential elements, hiding functionality with negligible delay overhead.
• Developed a locking EDA flow compatible with standard industrial tools and verified the technique on common benchmark circuits through multiple tape-outs in 16/22nm nodes.
• Extended existing attack methods to account for the technique and demonstrated exponentially increasing attack times with minimal PPA overhead.

Technical

• Languages: Python, Tcl, C/C++
• HDL: SystemVerilog, Verilog, Chisel, FIRRTL
• Tools: Cadence Genus/Innovus/JasperGold/Virtuoso, Calibre DRC/LVS/PEX, Mentor Tessent, Xilinx Vivado
• Software: Built and help maintain circuitgraph, a Python library for the manipulation of Boolean circuits.

Publications

• Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion
  P. Mohan, O. Atli, J. Sweeney, O. Kibar, L. Pileggi and K. Mai
  Design and Test in Europe (DATE-21), February 2021.
• Modeling Techniques for Logic Locking
  J. Sweeney, M. J. H. Heule, and L. Pileggi
  International Conference on Computer Aided Design (ICCAD-39), November 2020.
• Split-Chip Design to prevent IP Reverse Engineering
  S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra, and L. Pileggi
  IEEE Design & Test, October 2020.
• Sensitivity Analysis of Locked Circuits
  J. Sweeney, M. J. H. Heule, and L. Pileggi
  International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.
• Latch-Based Logic Locking
  J. Sweeney, M. V. Zackriya, S. Pagliarini, and L. Pileggi
  International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.
• Latch-Based Logic Locking
  J. Sweeney, S. Pagliarini, and L. Pileggi
  Government Microcircuit Applications and Critical Technology Conference (GOMACTech-20), March 2020.
• Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization
  F. Sadi, J. Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, and F. Franchetti.
  International Symposium on Microarchitecture (MICRO '52), October 2019.
• Securing Digital Systems via Split-Chip Obfuscation
  J. Sweeney, S. Pagliarini, and L. Pileggi
  Government Microcircuit Applications and Critical Technology Conference (GOMACTech-19), March 2019
• PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
  F. Sadi, J. Sweeney, S. McMillan, T. M. Low, J. Hoe, L. Pileggi, F. Franchetti,
  IEEE HPEC Graph Challenge, September, 2018
• A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ
  S. Bhuin, J. Sweeney, S. Pagliarini, A. K. Biswas and L. Pileggi
  International Symposium on Nanoscale Architectures (NANOARCH), July 2017

Co-Curricular

• The CUT Magazine Writing Staff
  October, 2016
  November, 2016
• CMU ECE Graduate Organization
• Columbia University Club Hockey
• Tau Beta Pi Engineering Honors Society